Is CISC really more convenient for writing assembly by hand? In x86_64 i was always short on registers. And using arguments from memory wasn't all that useful, because I often needed them more than once.
Also, while on a VAX this wouldn't be a problem, x86_64 has a few peculiarities wrt. when you can use which addressing mode. It's not orthogonal at all.
Hm... trying to remember what it was like to write ARM assembly, and IIRC I kinda missed register+scale*index+offset addressing for loads.
I should try writing MIPS assembly some day
@wolf480pl Same here. Always think register+scale*index+offset is more straightforward.
@dinoallosaurus IMO not more straightforward, but more convenient.
And in Intel syntax it's definitely more intuitive that ARM's bit-shift syntax, not to mention ARM's funny post-increment/decrement.
If you know the conditions in which ARM was initially designed, it all makes sense, but otherwise it's pretty weird...
@wolf480pl Agree. I had a better time understanding and using intel syntax. So I think that's why I got the feeling of it being simpler.
@wolf480pl I found 68000 to be incredibly nice to use. It's a CISC architecture with 16 registers available to the programmer. I did at times feel like I was running out of registers, but not too often.
On the other hand, I have used SPARC as well, which is a RISC architecture with a lot of registers (it uses register windows so you can have hundreds of registers, although only 31 are visible at any time, and they are split into 4 groups).
What's I'm saying here is that availability of registers isn't related to the CISC vs. RISC definitions.
>availability of registers isn't related to the CISC vs. RISC definitions.
It's not in the definition because there is no definition AFAIK, only a vague concept.
But it's correlated.
CISC CPUs *tend to*:
- have fewer registers
- have a larger part of the registers designated to specific purpose
- have more addressing modes
- make addressing modes available in arithmetic instructions
- have more high-level instructions
- have larger variance in instruction latency
@wolf480pl I agree with all of those except for the one about register count. I can't really think of a CISC architecture with a limited number of registers other than x86. That said, I'm not going to claim that I know all (or even most) instruction sets out there 🙂
Though you could argue that it's not a CISC, it's just cheap.
I'd expect a large number of general-purpose registers to be a consequence of a load-store design, where most instructions are register-to-register, and the only instructions that touch memory are load and store.
@wolf480pl So perhaps it can be concluded that while RISC CPU's need a reasonable amoun tof registers in order to be efficient, a CISC CPU can get away with fewer?
@loke hmm... looks like VAX had 16 registers as well, and according to wikipedia, 68k is very similar to VAX
@wolf480pl Yes. That's the first thing that I noticed when I was looking at VAX.
VAX is a bit more powerful than 6800 though. It has instructions for search linked lists, if I'm not mistaken which can be useful for a Lisp implementation?
@loke just realized I only read about VAX's addressing modes, and never went on to find out what instructions it has. But the addressing modes are so cool...
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